1. Field of the Invention
The present invention relates to a MOS semiconductor memory device, and more particularly to a structure of a MOS semiconductor memory device used as a mask MOS for writing a program during a manufacturing process.
2. Description of the Related Art
A diffused layer program system, an ion implantation program system, a contact hole program system and the like are used for writing a program in a mask ROM. These systems are described in "Design of CMOS Super Large Scale LSIs" supervised by Takuo Sugano, published on Apr. 25, 1989 by Baifukan, pp. 168-169. As to a cell area per bit, a mask ROM by the ion implantation program system has the smallest area, and a series type arrangement can be adopted therein.
FIG. 7 shows a schematic partial plan view of a conventional series type mask ROM by the ion implantation program system, and FIG. 8 shows an equivalent circuit diagram of that mask ROM. Source and drain diffused layers of MOS transistor 72 serve as a bit line 54, and each word line 52 is formed in a direction perpendicular to the bit line 54. Thus, an arrangement where the channel direction of the MOS transistor 72 forming a respective memory cell coincides with the direction of the bit line 54 is obtained. Programming is performed normally in such a manner that the threshold voltage (hereinafter abbreviated as Vth) of each of MOS transistor 72 is set in an enhancement type in advance, and only the Vth of the selected MOS transistors 72 is changed over to a depletion type by an ion implantation method for programming. In FIG. 7, 82 represents an isolation insulator, and, in FIG. 8, 62 represents a row decoder and 64 represents a column decoder.
In order to read data out of a memory cell, all the word lines are initially made at a high level and then the selected word line 52 is brought to a low level and the selected bit line 54 is brought to a high level. At this time, when the Vth of the selected memory cell is of a depletion type, an electric current flowing in the selected bit line 54 is kept flowing even if the word line 52 is brought to the low level. On the other hand, if the Vth is of an enhancement type, the electric current flowing through the selective bit line 54 is cut off. The data is read out by the method described above.
Further, FIG. 9 shows a circuit diagram of a conventional parallel type mask ROM. The circuit is structured so that a bit line 56, a MOS transistor 72 and a bit line 58 are arranged in this order repeatedly in the row direction. A drain and a source of each of the MOS transistors 72 arranged in the column direction are connected to left and right bit lines 56 and 58, and gates of the MOS transistors arranged in the row direction are connected to the same word line 52. The bit lines 56 are all grounded electrically, and selection of one of the columns is made by means of the bit lines 58.
In the case of the parallel type structure, the Vth of each MOS transistor 72 is set to an enhancement type to such an extent that the MOS transistor is turned on when the gate (word line 52) of the MOS transistor 72 is brought to a high level at time of data readout. The programming is performed by changing only the Vth of the selected memory cell by the ion implantation method to such a value that the MOS transistors 72 is not turned ON even if the word line is brought to a high level. In order to read data out of the memory cell all the word lines 52 are initially kept at a low level or opened and the bit line 58 are also kept opened. Then, only the selected word line 52 is brought to a high level, and selection of one of the columns is made by means of the bit lines 58. The memory cell is selected in such a manner for reading the data thereof through a sensor 66.
The series type mask ROM is widely used in general, since the cell size can be made smallest. Since respective MOS transistors 72 arranged in the column direction are connected in series directly to the bit line 54, however, there is the problem that the source of the MOS transistor 72 is not directly coupled with the substrate potential and hence the Vth of the transistor rises by the body effect. Moreover, as the number of the MOS transistors 72 connected in series in the column direction is increased, the total channel conductance thereof gets smaller. Therefore, there is also the problem that the reading current is restricted, and the reading speed becomes slower.
On the other hand, in the parallel type mask ROM, the sources of respective MOS transistors 72 are always grounded through the bit lines 56, and no influence by the body effect is exerted. In addition, even if the number of the MOS transistors 72 connected in the column direction is increased, the reading current flowing through to the bit line 58 is not restricted. Thus, it is possible to solve the problems of the series type mask ROM. Since two bit lines 56 and 58 are required for each memory cell, however, the memory cell size becomes larger, thereby making it difficult to integrate the memory cells at high density. A conventional parallel type mask ROM is disclosed in JP-A-63-127,496 for instance.